Design on ESD Protection Circuit with Very Low and Constant Input Capacitance
نویسندگان
چکیده
Research Motivation Effective on-chip ESD design to solve the ESD protection challenge on the analog pins for highfrequency or current-mode applications is studied. The device dimension of ESD clamp devices in analog ESD protection circuit can be reduced to have a much small input capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD level. To find the optimized device dimensions and layout spacings on ESD clamp devices, a design model is developed to keep the input capacitance as constant as possible (within 1% variation).
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Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work to keep the total input capacitance almost constant, even if the analog signal has a varying input voltage. An analog ESD protection circuit has been designed to solve ESD protection challenge on the analog pins for highfrequency applications. The device dimension ...
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